A (255,223) 8-bit Reed-Solomon (RS) code in concatenation with a (7, 1/2) Viterbi-decoded convolutional code has been recommended by the CCSDS (Consultative Committee for Space Data System) as a standard coding system for down link DSN (Deep Space Network) telemetry system. FIG. 1 shows a CCSDS recommended DSN transmission system. This concatenated coding system provides a coding gain of about 2 dB over the (7, 1/2) Viterbi-decoded only system.
Software simulations show that a (1023, 959) code, when concatenated with a (15, 1/6) Viterbi-decoded convolutional code, provides another 2 dB coding gain over the standard system recommended by CCSDS. This additional coding gain may be needed for future deep space missions to save cost since coding is among the most cost efficient way to improve system performance. A VLSI-based (15, 1/6) Viterbi decoder is currently being developed at the Jet Propulsion Laboratory to support the Galileo project and is expected to operate by 1991. Therefore, a (1023, 959) RS decoder is needed to provide the remainder of the 2 dB coding gain.
Recently, several VLSI architectures for implementing RS decoders have been proposed. However, the complexity of a RS decoder increases with the symbol size of the code. It is very unlikely that a RS decoder which can correct both errors and erasures will be implemented on a single chip in today's technology if the symbol size of the code is larger than 8 bits.
The existing VLSI RS decoders use a natural scheme to partition the decoder system. In this natural partitioning scheme, as many functional blocks in a RS decoder system are grouped together as possible and realized on the same VLSI chip. For instance, the VLSI chip set developed by the University of Idaho has four different types of VLSI chips. (G. K. Maki, et al., "VLSI Reed-Solomon Decoder Design," Proceedings of the Military Communications Conference (Milcom), Monterey, Calif., pp. 46.5.1-46.5.6, Oct. 5-9, 1986.) The first chip computes the syndromes. The second chip is the Euclid miltiply/divide unit. The third chip performs as a polynomial solver. The final chip is the error correction chip. This kind of partitioning scheme is straightforward. However, it is expected that several different types of VLSI chips are required to implement a RS decoder of symbol size larger than 8 bits.
The costs to design, fabricate and test VLSI-based systems increase drastically with the number of different chip types used. As an example, the (255, 223) error-correcting only RS decoder developed by the University of Idaho consists of four different types of VLSI chips, as just noted above. Assuming it takes 8 work-months to design and test a VLSI chip, which is a reasonable assumption for a VLSI chip of this complexity, four different chips require 32 work-months to develop. Furthermore, assuming it costs $80,000 to fabricate a VLSI chip of this complexity, the total VLSI chip fabrication cost of the above RS chips is $320,000. By utilizing the concept of the present invention, it takes only 8 work-months to design and test and $80,000 fabrication cost to develop VLSI chips for the single chip to be replicated for an RS decoder system. Based on the above analysis, a single-chip type RS decoder system is expected to have a five fold cost savings compared to RS decoder systems using conventional partition schemes.
As noted hereinbefore, the (255, 223) 8-bit RS code has been recommended by the CCSDS as part of the standard coding scheme in the DSN telecommunication system. Software simulations also show the system performance improvement obtained by concatenating a (1023, 959) 10-bit RS decoder with a (15, 1/6) Viterbi decoded convolutional code. Therefore, there is a need for developing both 8-bit and 10-bit RS decoders for current and future uses. As a consequence, it is desirable to realize an RS decoder which is capable of being switched between 8-bit and 10-bit codes. The key in developing such an 8-bit and 10-bit switchable RS decoder is the development of an 8-bit and 10-bit switchable finite field multiplier which is the most frequently used functional building block in an RS decoder.